(1) Field of the Invention
The invention relates to a method of passivation in the fabrication of integrated circuits, and more particularly, to a method of passivation which will both eliminate metal voiding and improve metal electromigration lifetime in the fabrication of integrated circuits.
(2) Description of the Prior Art
The conventional top metal passivation scheme is a sandwich layer comprising silicon oxynitride, spin-on-glass, and a top layer of silicon nitride. However, after the complete thermal cycle, a void may be found in the metal line.
For example, FIG. 1 illustrates a partially completed integrated circuit device. Top metal lines 20 are shown. Layer 16 on the semiconductor substrate contains all of the semiconductor device structures and lower level metallization, not shown in detail here. First dielectric layer 22 comprises silicon oxynitride having a thickness of about 1500 Angstroms. A spin-on-glass layer or layers 24 fills the gaps between the metal lines. The top dielectric layer 26 comprises silicon nitride deposited by plasma-enhanced chemical vapor deposition (PECVD) to a thickness of between about 7000 and 10,000 Angstroms. Scanning electron microscope (SEM) pictures show the presence of metal voids 30 when this conventional passivation scheme is used. Jmax is one index of electromigration lifetime. It is desirable to have a Jmax of at least 1.6 mA/.mu.m. The top metal line Jmax using the conventional process is between about 0.5 and 1.0 mA/.mu.m. The void 30 has been seen to be larger than half the size of the metal line.
The inventors have discovered that the metal voiding is a stress-induced void caused by thermal shrinkage of the spin-on-glass layer after the complete thermal cycle has been run. It has been discovered that the spin-on-glass shrinks by about 8% which induces metal voiding. It is desired to find a non-shrinkable passivation scheme to eliminate metal voiding and improve electromigration lifetime.
U.S. Patent 5,681,425 to Chen teaches gap filling by a series of deposition and etching cycles using PECVD TEOS (tetraethoxysilane) oxide and a top passivation layer of silicon nitride. U.S. Patent 5,851,603 to Tsai et al discloses a passivation layer comprising oxide/nitride/oxide/nitride. The oxide could be a high density plasma (HDP) oxide. U.S. Patent 5,759,906 to Lou discloses a multilayer passivation layer including a first PECVD TEOS oxide layer and a spin-on-glass layer wherein the sidewalls of a via through this layer are coated with a HDP fluoro-silicate glass (FSG) layer to prevent poisoned via contamination. U.S. Pat. No. 5,858,869 to Chen discloses a passivation layer comprising an anisotropic plasma oxide, a polymer, and a FSG layer deposited by HDPCVD. None of these patents mention the metal voiding problem.